D&T - Call for Papers for Special Issue on IR-drop in Deep Submicron

CALL FOR PAPERS

Scope -- Submission and Review Procedures

Scope

As technology shrinks scaling to 22nm and functional density continues to rise, many factors and parameters have shown direct impact on design and test of chips. IR-drop and power supply noise (PSN) effects have become more significant in recent years and need to be efficiently taken into consideration, as both cause design, test and reliability issues for the chip. Timing closure and functional verification cannot be considered to be complete until pre-and post-layout IR-drop, ground bounce, and PSN effect have been estimated and the appropriate margins applied. These effects have complex interdependencies and conventional design tools do not have the capability to consider all of these effects and their interrelationships concurrently. On-chip monitoring, careful power-ground network planning, worst-case IR-drop prediction, pattern generation for maximum supply noise, path delay analysis considering IR-drop and PSN are among the strategies and methods that should be used. The IEEE Design & Test of Computers seeks original manuscripts for a special issue on IR-drop and power supply noise effects on design and test of very deep submicron designs, scheduled for publication in June 2007. The topics of interest include, but are not limited to:

IR-drop effect on path delay test, IR-drop effects during faster-than-at-speed test
Power management during launch and capture of at-speed test
IR-drop and power supply noise measurement, Pattern generation for worst-case IR-drop and power supply noise
IR-drop and PSN aware timing verification, Library characterization for IR-drop aware performance verification
On-chip monitoring of power supply noise
Power grid verification ensuring target chip performance, Power and timing closure in presence of IR-drop and PSN
Reliability issues of excessive noise on chip, Minimization of power supply noise, full-chip hot spot identification
Decoupling capacitance allocation for PSN suppression, optimization of decap, New packaging methods
Process variations effect on IR-drop and PSN, Aging effect of IR-drop and PSN, Signal integrity

Submission and Review Procedures

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Prospective authors should follow the submission guidelines for the IEEE Design & Test of Computers. Authors must indicate that their manuscript is being submitted to the Special Issue on “IR-drop in Deep Submicron”. All manuscripts must be submitted electronically to the IEEE manuscript central web site at http://www.manuscriptcentral.com/. All papers will undergo the standard IEEE D&T review process.

Schedule

Submission Deadline: October 31, 2006
Reviews Completed: December 21, 2006
Revisions Due (if necessary): January 10, 2007
Reviews of Revisions Completed (if necessary): February 9, 2007
Notification of Final Acceptance: February 12, 2007
Submission of Final Version: February 24, 2007
Target Publication Date: May/June 2007

Guest Editors:

Mohammad Tehranipoor
Electrical and Computer Eng. Department
University of Connecticut
Storrs, CT
tehrani@engr.uconn.edu

Kenneth M. Butler
Silicon Technology Development
Texas Instruments
Dallas, TX
kenb@ti.com

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	*Design & Test of Computers* Special Issue on IR-Drop and Power Supply Noise Effects on Design and Test of Very Deep Submicron Designs http://www.computer.org/dt/